1. Field of the Invention:
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device in which a signal delay at a lower level line made of a material having a comparatively high resistance and high melting point, such as polysilicon, is compensated by an upper level line made of a material having a comparatively low resistance, such as aluminum. The present invention also relates to a process for fabricating such a semiconductor device.
2. Description of the Prior Art:
Since the packing density of a semiconductor device in which a number of semiconductor elements are integratedly formed on one chip has been enlarged, the length of wiring interconnecting the elements on the chip has been increased. On the other hand, the width of the wiring has been reduced so as to enhance the packing density. Generally, a long and narrow wiring has a high resistance. Wiring having a high resistance causes a problem of signal delay, which reduces the operation speed of the semiconductor device.
In a dynamic random access memory (DRAM), material having a low resistance and low melting point such as aluminum can not be used for a word line because it is not durable in the fabricating process of the semiconductor device. Instead, a material having a relatively high resistance and high melting point such as polysilicon and polycide is used. In such a DRAM, in order to prevent the problem of signal delay that occurs at the word line, another wiring made of aluminum is formed above the word line so as to run substantially in parallel with the word line. This aluminum wiring, called a "backing line", is connected to the word line at a plurality of points.
A conventional semiconductor device provided with the backing line will be described in detail. FIGS. 5A and 5B show partial sectional views of such a conventional semiconductor device. The semiconductor device has a structure of stacked capacitor cells. Referring to FIG. 5A, a part of the semiconductor device shown as B (right side of the dash-dot line in the figure) is a memory cell region having a plurality of memory cells. The other part of the semiconductor device shown as A (left side of the dash-dot line in the figure) is a memory cell peripheral region surrounding the memory cell region B. In the memory cell region B, a plurality of MOSFETs and memory capacitors connected to the respective MOSFETs are arranged in a matrix.
FIG. 6 schematically shows four memory cell regions B and the memory cell peripheral regions A surrounding these memory cell regions B. Each memory cell region B includes 256.times.64 memory cells arranged in a matrix. Each of the memory cells is connected to a word line 4 and a bit line 8. Thus, totally 256 word lines 4 and 64 bit lines 8 run through one memory cell region B. Each word line 4 and an aluminum backing line 15 running in parallel with the word line 4 are connected to each other in the memory cell peripheral region A, not in the memory cell region B. Sense amplifiers are also disposed in the memory cell peripheral region A.
Referring to FIGS. 5A and 5B, the structure of the conventional semiconductor device will be described. The semiconductor device comprises a semiconductor substrate 1, a level of the word lines 4, a level of the backing lines 15, and a level of bit lines 8 disposed between the above two levels. The bit lines 8 run transversely to the direction of the word lines 4 and the backing lines 15 (FIG. 6). Each bit line 8 is composed of a polysilicon film 8a as a lower layer and a silicide film 8b as an upper layer.
A field oxide film 2 is formed between the semiconductor substrate 1 and the word lines 4. As shown in FIG. 5B, each word line 4 is covered with an upper insulating film 5 on the top surface thereof and with side-wall insulating films 6 on the sides thereof. A first interlevel insulating film 18 is formed between the word lines 4 and the bit lines 8 for insulating them from each other. The bit lines 8 are electrically connected to sources of transistors in the memory cell region B through respective contact holes (not shown) formed through the first interlevel insulating film 18.
A second interlevel insulating film 9 is formed over the first interlevel insulating film 18 so as to cover the bit lines 8. On the second interlevel insulating film 9 in the memory cell region B, memory capacitors comprising storage nodes 10, capacitor insulating films 11, and a plate electrode 12a are formed. Each storage node 10 is connected to a drain (not shown) of the corresponding transistor.
A third interlevel insulating film 13 is formed over the second interlevel insulating film 9 so as to cover the plate electrode 12a. In the memory cell peripheral region A, contact holes 17 having a high aspect ration are formed through the interlevel insulating films 13, 9, and 18 and the upper insulating film 5 to reach the word lines 4. Each contact hole 17 has a tungsten (W) plug 14 formed therein. Thus, each aluminum backing line 15 having a low resistance is electrically connected to the corresponding word line 4 through the tungsten plug 14. The backing line 15 runs above the word line 4 substantially in parallel therewith.
As described above, the memory cell region B includes the bit lines 8 (thickness: about 240 nm), the storage nodes 10 (thickness: about 500 nm), the capacitor insulating films 11 (thickness: about 5 nm), and the plate electrode 12a (thickness: about 100 nm), which are not formed in the memory cell peripheral region A. Therefore, the third interlevel insulating film 13 in the memory cell region B is formed in a higher position than that in the memory cell peripheral region A by the total thickness of the above layers (about 845 nm), producing a step of that height at the boundary between the memory cell region B and the memory cell peripheral region A. This step causes the following problems in the photolithography and etching processes:
(1) Since the height of the step exceeds the allowable depth of focus for the photolithography (normally, no more than about 800 nm), a precise focusing on both the memory cell region B and the memory cell peripheral region A is not possible. Thereby, it is difficult to form a fine resist pattern on the semiconductor device.
(2) An aluminum film formed by sputtering on the vertical side of the step portion is thinner than that on the flat portion. Thereby, the reliability of the aluminum backing line 15 including such a thin film portion is lowered.
(3) The thickness of the aluminum film in the direction vertical to the substrate 1 is larger at the step portion than at the flat portion. Therefore, after the aluminum film is etched by a high anisotropic etching method, some aluminum tends to be left behind on the side of the step portion. Such aluminum left behind on the side of the step portion may cause a short circuit between the aluminum backing lines 15.
(4) Tungsten (or polysilicon) is deposited on the entire surface of the third interlevel insulating film 13 and then etched back so as to form a CVD tungsten plug (or a CVD polysilicon plug) inside the contact hall 17 by a blanket method. After the etching back, some of the tungsten (or the polysilicon) tends to be left behind on the step portion.
Further, in the conventional semiconductor devices, the aspect ratio of the contact hole 17 for connecting the aluminum backing line 15 with the word line 4 is high (about 3.5 to 5.0). It is difficult to form the tungsten plug 14 through the contact hole 17 having a high aspect ratio.